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LP5521
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CONFIGURATION CONTROL (CONFIG)
Address 08H
Reset value 00H
Table 28. CONFIG Register
SNVS441F – JANUARY 2007 – REVISED FEBRUAY 2013
7
6
PWM_HF
5
PWRSAVE_EN
4
CP_MODE[1:0]
3
2
R_TO_BATT
1
CLK_DET_EN
0
INT_CLK_EN
Name
Bit
Access
Active
Description
PWM clock
PWM_HF
6
R/W
High
0 = 256 Hz PWM clock used (CLK_32K)
1 = 558 Hz PWM clock used (internal oscillator)
PWRSAVE_EN
5
R/W
High
Power save mode enable
Charge pump operation mode
00b = OFF
CP_MODE
4:3
R/W
01b = Forced to bypass mode (1x)
10b = Forced to 1.5x mode
11b = Automatic mode selection
R channel supply connection
R_TO_BATT
2
R/W
High
0 = R output connected to charge pump
1 = R output connected to battery
LED Controller clock source
CLK_DET_EN,
INT_CLK_EN
1:0
R/W
00b = External clock source (CLK_32K)
01b = Internal clock
10b = Automatic selection
11b = Internal clock
R CHANNEL PROGRAM COUNTER VALUE (R CHANNEL PC)
Address 09H
Reset value 00H
Table 29. R Channel PC Register
7
6
5
4
3
2
1
0
R_PC[3]
R_PC[2]
R_PC[1]
R_PC[0]
Name
R_PC
Bit
3:0
Access
R/W
Active
Description
R channel program counter value
PC registers are synchronized to 32 kHz clock. Delay between consecutive I 2 C writes to PC registers needs to
be longer than 153 μ s (typ.). PC register can be read or written only when EXEC mode is 'hold'.
Copyright ? 2007–2013, Texas Instruments Incorporated
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